1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device having a Delayed Locked Loop (DLL) circuit.
Recently, both the operation speed and integration density of semiconductor integrated circuit devices have increased considerably, and it has become necessary to supply phase-synchronized clock signals to predetermined circuits within the semiconductor integrated circuit devices. More particularly, in a Synchronous Dynamic Random Access Memory (SDRAM), a DLL circuit is used to supply a clock signal which is phase-synchronized to an external clock signal to a plurality of output buffer circuits. In order for the DLL circuit to cope with a high-frequency clock signal, it is necessary to use a digital DLL circuit which operates at a high precision.
2. Description of the Related Art
FIG. 1 is a system block diagram showing an example of a conventional DLL circuit. In FIG. 1, external clock signals /CLK and CLK having mutually inverted phases are respectively input to input terminals 150 and 151, and supplied to delay circuits 154 and 155 via input buffers 152 and 153. In addition, the external clock signal CLK output from the input buffer 153 is supplied to a phase comparing section 157 within a phase comparator 156, as a reference clock.
The external clock signal CLK output from the input buffer 153 is passed through the delay circuit 155, a dummy output buffer 160 and a dummy input buffer 161 and delayed, before being supplied to the phase comparing section 157. The dummy output buffer 160 has the same circuit construction as an output buffer 162, and the dummy input buffer 161 has the same circuit construction as the input buffers 152 and 153. The phase comparing section 157 compares phases of the clock signal which is delayed by the dummy input buffer 161 and the reference clock (clock signal CLK), and generates a phase error signal at the timing of a rising edge of the clock signal CLK. This phase error signal is supplied to delay control circuits 164 and 165 via respective amplifier sections 158 and 159. The amplifier section 158 synchronizes the phase error signal to the timing of a rising edge of the clock signal /CLK.
The delay control circuit 165 controls a delay quantity of the delay circuit 155 so as to eliminate the phase error, based on the phase error signal. Hence, the delay quantity of the delay circuit 155 is variably controlled so that the rising edge of the delayed clock signal matches the rising edge of the reference clock, that is, so that the delayed clock signal is delayed by a quantity corresponding to k periods of the external clock signal with respect to the reference clock. The constructions of the delay control circuit 164 and the delay circuit 154 respectively are the same as the constructions of the delay control circuit 165 and the delay circuit 155. The delay control circuit 164 similarly controls a delay quantity of the delay circuit 154 so as to eliminate the phase error, based on the phase error signal. As a result, the clock signals /CLK and CLK which are mutually inverted and delayed by the respective delay circuits 154 and 155 are supplied to the output buffer 162.
The output buffer 162 reads data in synchronism with the rising edges of the clock signals /CLK and CLK which have the mutually inverted phases. For this reason, in order to prevent noise from being generated at the rising edges of the clock signals /CLK and CLK, the delay control circuit 165 variable controls the delay quantity of the delay circuit 155 during a time t1 with respect to the clock signal CLK shown in FIG. 2(a), and the delay control circuit 164 variably controls the delay quantity of the delay circuit 154 during a time t2 with respect to the clock signal /CLK shown in FIG. 2(b). The amplifier section 158 synchronizes the timing of the phase error signal to the rising edge of the clock signal /CLK, so that the variably controlling timings of the delay control circuits 164 and 165 differ.
A DRAM (not shown) which supplies a read data DATA to the output buffer 162 carries out a high-speed access so that an apparent data read speed is doubled by reading the data in synchronism with each of two clock signals having mutually inverted phases. The output buffer 162 carries out a buffering operation with respect to the data on a data bus (not shown), in synchronism with the supplied clock signals /CLK and CLK and outputs a buffered data D.sub.OUT via a data output terminal 166.
But according to the conventional DLL circuit shown in FIG. 1, it is necessary to provide the delay control circuits 164 and 165 respectively with respect to the delay circuits 154 and 155, and there are problems in that a circuit scale and a required chip area of the DLL circuit become large.